The present invention relates generally to so-called diamond buffer amplifiers, and more particularly to diamond buffer amplifiers having substantially improved slew rate performance and high current gain at high frequencies.
FIG. 1 shows a simple prior art diamond buffer amplifier 1A, which is similar to well-known basic diamond follower circuits. In FIG. 1, an input signal Vin is coupled to the bases of a PNP input transistor Q4 and an NPN input transistor Q3. The emitter of input transistor Q3 is coupled by conductor 5 to a constant current source I1 and also to the base of a PNP output transistor Q2. Similarly, the emitter of input transistor Q4 is coupled by conductor 4 to a constant current source I2 and also to the base of an NPN output transistor Q1.
The current gain of diamond buffer amplifier 1A of FIG. 1 is βnpn×βpnp, which can be considered to be simply β2. In some cases, the current gain is too low because β2 is too low. Also, the current Iout delivered by diamond buffer amplifier 1A is limited by the value of I2×βnpn associated with sourcing current to the base of output transistor Q1, and because Iout also is limited by the value of I1×βpnp associated with sinking current from the base of output transistor Q2. (In theory, at maximum values of Iout, for either current sourcing or current sinking operation, all of the I2 or I1 current will go to the base of transistor Q1 or transistor Q2, respectively.) Low values of βnpn and βpnp also set a limit to the ratio of the quiescent current of diamond buffer amplifier 1A to the maximum value of output current Iout and therefore can limit the effectiveness of diamond buffer amplifier 1A. (The explanation for this is that if high Iout is desired and β is low, it is necessary to increase I2 and I1, thus increasing total quiescent current.) The slew rate of diamond buffer amplifier 1A is determined by the parasitic capacitances of the bases of output transistors Q1 and Q2 and by the currents I2 and I1 available to charge and recharge their parasitic base capacitances, respectively. (The base capacitances referred to consist mainly of the base-collector junction capacitances and also the amount of any load capacitance divided by β.)
FIG. 2 is a simplified schematic diagram of a diamond buffer amplifier 1B which is described in commonly owned U.S. Pat. No. 7,102,440 entitled “High Output Current Wideband Output Stage/Buffer Amplifier” issued Sep. 5, 2006 to Damitio et al. and incorporated herein by reference. Diamond buffer amplifier 1B is an improvement over the one shown in FIG. 1. Referring to FIG. 2, one of the prior art techniques for partially resolving the above-mentioned problems associated with low values of I2×βnpn and I1×βpnp (i.e., limiting the magnitude of Iout and limiting the ratio of the quiescent current of the diamond buffer amplifier to the maximum value of Iout) is to provide controlled current source circuits 11 and 10 in place of constant current sources I1 and I2, respectively. The controlled current sources 11 and 10 are implemented with transistors Q5 and Q6, respectively, and associated local current feedback loops which keep the operating currents of input transistors Q3 and Q4 stable while providing the bases of the output transistors Q1 and Q2 with the required amounts of current by adjusting the currents in transistors Q5 and Q6.
Controlled current source circuit 10, which replaces constant current source I2 of FIG. 1, includes PNP transistor Q6 and also includes a constant current source I6 connected between VCC and conductor 6. Conductor 6 also is connected to the collector of an NPN transistor Q8, the base of which receives a bias voltage Bias2. The emitter of transistor Q8 is connected by conductor 8 to the collector of input transistor Q4 and to a constant current source I4. Similarly, controlled current source circuit 11, which replaces constant current source I1 of FIG. 1, includes NPN transistor Q5 and also includes a constant current source I5 connected between VEE and conductor 7. Conductor 7 also is connected to the collector of a PNP transistor Q7, the base of which receives a bias voltage Bias1. The emitter of transistor Q7 is connected by conductor 9 to the collector of input transistor Q3 and to a constant current source I3.
As an example, if the input voltage Vin, and hence the output voltage Vout, go to a high voltage, output transistor Q1 sources the current Iout to the load (not shown), and the base current of output transistor Q1 increases, thereby “stealing” a portion of the emitter current of input transistor Q4. This causes the collector current of input transistor Q4 to decrease, which increases the collector current of transistor Q8 by the same amount of current lost to the base current of output transistor Q1. The increased collector current of transistor Q8 turns transistor Q6 on harder, which amplifies the additional current in the collector of transistor Q8 by the current gain β of transistor Q6. (The current gain β of transistor Q6 is the ratio of its collector current IC to its base current IB.) Transistor Q6 will then “reimburse” the current “stolen” from the collector of transistor Q4 and thereby return the operating current of input transistor Q4 to its normal level. Consequently, the current gain of the circuitry including transistors Q1, Q4, and Q6 is high, i.e., βQ4×βQ6×βQ1, for current sourcing operation. The term βQ4×βQ6×βQ1 can be considered to be simply β3. The current gain of the circuitry including transistors Q2, Q3 and Q5 is equal to βQ3×βQ5×βQ2 for current sinking operation, which also can be considered to be simply β3. The maximum output current is (I4−I6)×βQ6×βQ1 for current sourcing operation, and (I3−I5)×βQ5×βQ2 for current sinking operation, i.e., about one β factor better than for the circuit of FIG. 1. The controlled current sources 10 and 11 can also provide much higher slewing currents and therefore much better slew rates.
Still referring to FIG. 2, in a practical circuit the “local” feedback loops around the “pre-output” transistors Q5 and Q6 require some frequency compensation. An implementation of such frequency compensation is shown in FIG. 3, wherein the high impedance nodes at the base conductors 6 and 7 of controlled current source transistors Q5 and Q6 are slowed down with grounded compensation capacitors C1 and C2, and the transconductances (Gm) of transistors Q5 and Q6 are lowered by emitter degeneration resistors R1 and R2. The dominant pole frequency is lowered and “split” from a second pole associated with the base capacitances of the output transistors Q1 and Q2 and output resistances at the emitter nodes of the pre-output stage transistors Q3 and Q4. (Without frequency compensation, the first and second poles are too close together, just as in a typical operational amplifier structure there will insufficient phase margin. If the dominant pole is located closer to zero frequency so there is much larger separation between the dominant pole and the secondary pole, then adequate phase margin is obtained. note, however, that there is a distinction between the local loops that to be compensated and the overall operational amplifier loop, and that the present invention is not directed to compensating the overall operational amplifier.)
Unfortunately, the foregoing frequency compensation technique shown in FIG. 3 does not allow the currents in controlled current source transistors Q5 and Q6 to rise very fast to immediately deliver the maximum current and rapid recharging of the parasitic base capacitances of output transistors Q1 and Q2. As a result, the buffer amplifier 1C of FIG. 3 is not much better than the simple one shown in “Prior Art” FIG. 1 with regard to slew rate and current gain at high frequency.
Thus, there is an unmet need for buffer amplifier circuitry that provides a high slew rate and high current gain at high frequencies.
There also is an unmet need for a diamond buffer amplifier that provides a high slew rate and high current gain at high frequencies.